Field effect transistors are comprised of a pair of diffusion regions, referred to as a source and a drain, spaced apart within a semiconductive substrate. The transistors include a gate provided adjacent a substrate separation region between the diffusion regions for imparting an electric field to enable current to flow between the diffusion regions. The substrate material adjacent the gate and between the diffusion regions is referred to as the channel.
The semiconductive substrate typically comprises bulk crystalline silicon having a light conductivity doping impurity concentration of opposite type to the predominate doping of the source and drain regions. Alternately, the substrate can be provided in the form of a thin layer of lightly doped semiconductive material over an underlaying insulating layer. Such are commonly referred to as semiconductor-on-insulator (SOI) constructions. In the context of this document, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
Integrated circuitry fabrication technology continues to strive to increase circuit density, and thereby minimize the size and channel lengths of field effect transistors. Improvements in technology have resulted in reduction of field effect transistor size from long-channel devices (i.e., channel lengths greater than two microns), to short-channel devices (i.e., channel lengths less than two microns), and to sub-micron devices (i.e., channel lengths less than one micron). As field effect transistor channel lengths (i.e., gate or word line widths) became smaller than two microns, so-called short-channel effects began to become increasingly significant. As a result, device design and consequently process technology had to be modified to take these effects into account so that optimum device performance could continue to be obtained. For example, the lateral electrical field in the channel region increases as a result of smaller transistor channel lengths as the supply voltage remains constant. If the field becomes strong enough, it can give rise to so-called hot-carrier effects. Hot-carrier effects often lead to gate oxide degradation, as energetic carriers can be injected into gate oxide and become permanent charges.
Two recognized solutions to this problem, used either alone or in combination, include source/drain re-oxidation and provision of lightly doped drain (LDD) regions. Source/drain re-oxidation effectively grows a layer of thermal oxide over the source and drain areas as well as over the gate sidewalls. The oxidation has the effect of rounding the poly gate edge corners in effectively oxidizing a portion of the gate and underlying substrate, thereby increasing the thickness of the gate oxide layer at least at the edges of the gate. Such reduces the gate-to-drain overlap capacitance, and strengthens the gate oxide of the polysilicon gate edge. The latter benefits are effectively obtained because oxidation-induced encroachment gives rise to a graded gate oxide under the polysilicon edge. The thicker oxide at the gate edge relieves the electric-field intensity at the corner of the gate structure, thus reducing short-channel effects.
An example technique for accomplishing such re-oxidation includes conventional wet and dry oxidations at atmospheric pressure and at a temperature of800° C. or greater. Typical process exposure time is 10 minutes, which also grows a layer of oxide from 50 to 200 Angstroms thick on the sidewalls of the patterned gate.
LDD regions are provided within the substrate relative to the channel region in advance of the source and drains, and further reduce hot-carrier effects. The LDD regions are provided to be lighter conductively doped (i.e., less concentration) than the source and drain regions. This facilitates sharing the voltage drop between the drain and the channel, as opposed to the stark voltage drop at the channel occurring in non-LDD transistors. The LDD regions absorb some of the voltage drop potential into the drain, thus effectively eliminating hot-carrier effects. As a result, the stability of the device is increased.
Most commonly, a combination of source/drain re-oxidation and formation of LDD regions is utilized. However in combination, these processes can create problems, particularly in fabrication of sub-micron devices.
For example, consider FIGS. 1-2. FIG. 1 depicts a semiconductor wafer fragment 10 comprised of a bulk monocrystalline substrate 12 having a gate structure 14 formed thereover. Gate 14 comprises a gate oxide layer 16, an overlying conductively doped polysilicon layer 18, an overlying refractory metal silicide layer 20, and an insulative cap 22, such as Si3N4. That region beneath gate oxide layer 16 within bulk substrate 12 will constitute the channel region of the resultant transistor. Unfortunately when subjected to source/drain re-oxidation, the differing materials of gate 14 do not oxidize at the same rate. FIG. 2 illustrates an oxide layer 24 formed over substrate 12 and the sidewalls of gate structure 14 after a source/drain re-oxidation. Silicide layer 20 of gate structure 14 has a tendency to oxidize at a significantly greater rate than the oxidation of either nitride layer 22 or polysilicon layer 18. Such results in the formation of the illustrated sidewall bulges 25.
The typical manner by which LDD regions are fabricated is by ion implantation of conductivity dopant impurity after source/drain re-oxidation, such as regions 26. Unfortunately, oxide bulges 25 in layer 24 effectively function as a mask to such ion implantation. This results in formation of LDD implant regions 26 being laterally spaced outwardly away from the original sidewalls of gate structure 14. This is undesirable. More preferably, the inner lateral edges of LDD regions 26 are desirably as close to the gate edges as possible.
The invention was principally motivated in overcoming drawbacks such as that described above with respect to field effective transistors fabrication. The artisan will, however, appreciate applicability of the following invention to other aspects of semiconductor wafer processing in formation of other electronic components or devices, with the invention only being limited by the accompanying claims appropriately interpreted in accordance with the Doctrine of Equivalents.